Experimental Investigations of the Stability of Candidate Materials for High-K Gate Dielectrics in Silicon-Based MOSFETs

Susanne StemmerCorresponding Author Contact Information, E-mail The Corresponding Author, a, Darrell G. Schlomb

aMaterials Department, University of California, Santa Barbara, CA 93106-5050, USA
bDepartment of Materials Science and Engineering, Penn State University, University Park, PA 16802-6602, USA.


Due to the continuous decrease in feature size, silicon devices are approaching a number of fundamental limits. In particular, the gate oxide in modern integrated circuits has reached atomic dimensions. When the thickness of the traditionally used gate dielectric material, SiO2, falls below ~1 nm, it has excessive leakage currents due to direct tunneling. Use of alternative gate oxides with higher dielectric constant (K) could permit similar transistor performance with drastically reduced leakage currents due to the greater physical thickness of the gate dielectric. Although they have been predicted to be thermodynamically stable in contact with silicon, these alternative oxides show a number of stability problems, in particular when exposed to high temperature anneals, which are typically around 1000oC. This chapter provides a description of the thermodynamic basics of high-K / silicon interface stability and of phase separation in silicate alloys. In addition, analytical experimental methods with high spatial resolution are essential in understanding the physical mechanisms of interfacial reactions and stability in these ultrathin layers. Such methods are discussed and experimental investigations of the stability of high-K / silicon interfaces are presented.

Author Keywords: Gate oxide, alternative gate dielectrics, thin films, ZrO2, HfO2, silicate, CMOS, phase diagrams, spinodal decomposition, transmission electron microscopy.

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