Nanometer scale linewidth control during etching of polysilicon gates in high-density plasmas

O. JoubertCorresponding Author Contact Information, E-mail The Corresponding Author, E. Pargon, J. Foucher, X. Detter, G. Cunge and L. Vallier

Laboratoire des Technologies de la Microelectronique, CNRS, 17 Rue des Martyrs (CEA-LETI), 38054, Grenoble Cedex 9, France

Available online 24 June 2003.


We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition.

Author Keywords: Plasma etching; Gate patterning; CMOS scaling; Critical dimension control

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