Abstract

Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO₂ at conventional temperatures (near 620 °C) results in (1) a low density of large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO₂ films using metal gates or silicon gates with low temperature deposition. However, depositing conventional CVD poly-Si gates directly onto Al₂O₃-capped, hafnium–silicate-capped, or physical vapor deposition (PVD) silicon-capped HfO₂ resulted in the absence of large inhomogeneous poly-Si grains and well behaved capacitors with leakage reduction greater than 10³ times compared to the poly-Si/HfO₂ and poly-Si/SiO₂ controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO₂ are attributed to a partial reduction of the HfO₂ by the poly-Si deposition ambient. In the first case (1) the partial reduction occurs locally on the HfO₂ surface, forming Hf–Si_x bond(s) which act as nucleation points for crystalline silicon growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.

Author Keywords: HfO₂; Al₂O₃; Hafnium silicate; Hafnium aluminate; Dielectric

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