Bandgap and strain engineered Si–Ge–C vertical and planar MOSFETs

Sanjay BanerjeeE-mail The Corresponding Author

Microelectronics Research Center, University of Texas, Austin, TX 78712-1100, USA

Available online 20 June 2003.


We will discuss the application of Si-Ge-C binary/ ternary alloy pseudomorphic strained layers (with dilute C levels of ~1%) grown by low-temperature ultra high vacuum chemical vapor deposition (UHVCVD) in novel, high-carrier-mobility strained vertical and planar P and N-channel MOSFETs. The main motivation for grafting Ge and C onto Si technology is that the use of such heterostructures enables one to do somewhat independent bandstructure and strain engineering (both compressive with Si-Ge and tensile with Si-C) to achieve enhanced transport properties. For example, we will show how bandgap engineering in novel vertical P-MOSFETs can be used to suppress the short channel effects, floating body effects, and improve the drive current. SiGe source/Si channel heterobarriers are used to suppress leakage effects in sub-100nm devices, while a SiGe/Si compressively strained, high mobility cap layer is used to provide higher drive current. The use of high-K gate dielectrics (HfO2 and ZrO2) on Si-Ge planar MOSFETs will be discussed, and the challenges and opportunities will be pointed out. Finally, the use of Si-Ge-C and high-K dielectrics in novel flash memory MOS devices with Si-Ge-C self-assembled quantum dot floating gates will be discussed. We will show that such approaches are promising in terms of low voltage/ low power programming of these cells, along with improved non-volatility.

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