As dimensions of ULSI devices continue to shrink at a phenomenal pace, novel materials are required for deep sub-micron high-performance logic and memory devices. This is especially true for gate dielectric, the heart of MOSFETs. The equivalent (i.e. normalized with respect to the dielectrics constant of SiO₂ films) thickness of the gate dielectric is on the order of 2 nm (and thinner) in the state-of-the-art devices and is projected to be close to 1 nm in a few years. Direct tunneling currents, reliability, boron penetration from poly-Si gate, mobility degradation, and other fundamental issues are of a serious concern for such ultrathin oxides. In the presentation, I will first briefly overview gate oxide scaling issues.[1] Near-future silicon oxynitride solutions will be reviewed in short next.[2] This will be followed by a discussion of high dielectric constant (high-K) materials.[3,4] Processing issues, materials properties, physical characterization and electrical behavior of advanced gate dielectrics will be addressed.

1. D.A. Buchanan, Scaling the Gate Dielectric: Materials, Integration and Reliability, IBM J. Res. and Develop. 43, 245 (1999).
2. M.L. Green, E.P. Gusev, R. Degraeve, and E. Garfunkel, Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectrics layers for silicon microelectronics: Understanding the processing, structure and physical and electrical limits, J. Applied Physics (Review). 90, 2057 (2001).
3. G. Wilk, R.M. Wallace, J.M. Anthony High-K gate dielectrics: Current Status and Materials Properties Considerations, J. Applied Physics (Review). 89, 5243 (2001).
4. E. P. Gusev, E. Cartier, D. A. Buchanan, M. A. Gribelyuk, M. Copel, H. Okorn-Schmidt, C. D'Emic, Ultrathin high-K metal oxides on silicon: Processing, characterization and integration Issues, Microelectronic Engineering 59, 341 (2001).